1. Field of the Invention
The present invention relates to a method of fabricating semiconductor memory devices, and more particularly, to a method for integrating volatile and non-volatile memory devices on a single chip.
2. Description of the Related Art
Generally, electronic systems in various applications require, in addition to data processing units, memory devices to store data therein and/or read data therefrom. For enhanced performance, an electronic system may need dynamic random access memory (DRAM) devices and flash memory devices functionally or physically together. In this case, it is common that a DRAM device is used as temporary storage, and a flash memory device is used to store firmware and nonvolatile data. Such a combination of DRAM and flash memory devices can boost the system performance.
Especially, in portable electronic products, such as laptops and palm computers, where battery lifetime is a limitation on the performance and functionality of electronic systems of the products, such a combination of DRAM and flash memory devices is desirable to enhance the system performance. In such electronic systems, power consumption is an important factor determining the battery lifetime.
In general, volatile memory devices, such as DRAM devices, have higher data access speed and lower power consumption than those of non-volatile memory devices, such as flash memory devices, when sizes of the volatile and non-volatile memory devices are substantially equal. For example, a typical 100MHz SDRAM has a burst data rate of about 200 MB/sec, while the read performance of a linear flash memory is only about 20 MB/sec. Also, the data read power consumption in the flash memory is about 1.6 times as large as that of the DRAM. Thus, the power consumption as well as the system performance of an electronic system can be enhanced by employing DRAM devices.
DRAM devices can be used as a xe2x80x9cshadowxe2x80x9d of flash memory devices. For example, some portion of the application codes and/or operating system codes can be copied into a DRAM device after the system is powered on. This would allow data drivers such as graphic data driver or soft-modem to run at a faster speed. Also, during updating the application codes that are stored in a flash memory, the system can continue its normal operation through accessing the DRAM device. In other words, updating the data in a flash memory can be performed concurrently or sequentially without compromising the system performance.
DRAM devices are also used to store volatile data such as system stack, scratch-pad variables, frame buffers, etc. Thus, more utilization can be implemented with DRAM devices, while data can be stored for a longer time period in flash memory devices. DRAM devices also provide high density data storage and wide bandwidth for data read and write.
Drawbacks in the DRAM devices include incapability of saving data during power is down. Refresh has to be performed frequently to preserve valid data. This refresh process not only consumes power but also interrupts the availability of the data when the system requests.
On the other hand, flash memory has the advantage of nonvolatility so that the memory can preserve stored data when the system is not in active use. For example, when the power is interrupted due to changing battery in a portable system, data stored in flash memory can be preserved.
In conventional semiconductor memory devices, however, DRAM and flash memory devices are equipped in an electronic system using multi-chip packages. Semiconductor memory devices having the DRAM and flash memory devices using the multi-chip packages have drawbacks such as high manufacturing cost, degradation of the system performance, decrease in the integration density, and so on. Semiconductor memory devices fabricated using the conventional multi-chip approach are degraded in their performance due to narrow bandwidth. This is because stand-alone chips in a multi-chip package have limitation in data input/output. Thus, such a limitation restricts the number of data bandwidth.
Therefore, a need exists for a semiconductor memory device having the advantages of the high data bandwidth and access speed of DRAM devices and nonvolatility and power saving of flash memory devices. It would be advantageous to provide a semiconductor memory device having volatile and non-volatile memory devices merged into a single chip. It is also desirable to provide a method of integrating volatile and non-volatile memory devices on a single chip using minimized process steps.
It is an object of the present invention to provide a semiconductor memory device having merged volatile and non-volatile memory devices on a single chip.
It is another object of the present invention to provide a method of merging volatile and non-volatile memory devices in a single chip through a simplified process.
It is still another object of the present invention to provide a method of fabricating volatile and non-volatile memory devices and support devices on a single chip using a process having minimized steps.
It is further object of the present invention to provide a semiconductor memory device with high integration density by integrating DRAM and flash memory devices and support devices in a single chip.
To achieve the above and other objects, the present invention provides a method for fabricating dynamic random access memory (DRAM) and flash memory cells on a single chip. A method of the present invention includes providing a silicon substrate; forming a trench capacitor for each of the DRAM cells in the silicon substrate; forming isolation regions in the silicon substrate, the isolation regions being electrically isolated from each other; forming first type wells for DRAM and flash memory cells at first predetermined regions of the silicon substrate by implanting a first type impurity in the first predetermined regions; forming second type wells for DRAM and flash memory cells at second predetermined regions in the first type wells by implanting a second type impurity in the second predetermined regions; forming oxide layers for DRAM and flash memory cells on the second type wells; forming gate electrodes for DRAM and flash memory cells on the oxide layers for DRAM and flash memory cells; and forming source and drain regions for DRAM and flash memory cells in the respective second type wells for DRAM and flash memory cells, in which the source and drain regions are associated with each of the gate electrodes for DRAM and flash memory cells. The method may further include forming first type wells for support devices in the silicon substrate by implanting the first type impurity; forming second type wells for support devices in the silicon substrate by implanting the second type impurity; and forming oxide layers for support devices on the first and second type wells for support devices. The method may also include forming gate electrodes for support devices on the oxide layers for support devices; and forming source and drain regions for support devices in the first and second type wells for support devices, in which the source and drain regions for support devices are associated with each of the gate electrodes for support devices.
In another aspect of the present invention, there is provided a method for fabricating DRAM and flash memory cells on a single chip, which includes providing a silicon substrate; forming isolation regions in the silicon substrate, the isolation regions being electrically isolated from each other; forming first type wells for DRAM and flash memory cells at first predetermined regions of the silicon substrate by implanting a first type impurity in the first predetermined regions; forming second type wells for DRAM and flash memory cells at second predetermined regions in the first type wells by implanting a second type impurity in the second predetermined regions; forming oxide layers for DRAM and flash memory cells on the second type wells; forming gate electrodes for DRAM and flash memory cells on the oxide layers for DRAM and flash memory cells; forming source and drain regions for DRAM and flash memory cells in the respective second type wells for DRAM and flash memory cells, the source and drain regions being associated with each of the gate electrodes for DRAM and flash memory cells; forming a contact on each of second type wells for DRAM cells; forming a stacked capacitor connected to the contact; and forming a plate electrode on the stacked capacitor, wherein the stacked capacitor and the plate electrode serve as a capacitance storage for a corresponding DRAM cell. The method preferably further includes forming n-wells and p-wells for support devices in the silicon substrate; forming oxide layers for support devices on the n-wells and p-wells for support devices; and forming gate electrodes for support devices on the oxide layer for support devices.
According to another aspect of the present invention, there is provided a semiconductor memory device including a silicon substrate, DRAM cells each formed at respective first predetermined regions of the silicon substrate, flash memory cells each formed at respective second predetermined regions of the silicon substrate, isolation regions formed in the silicon substrate to electrically isolate the DRAM and flash memory cells from each other, and a trench capacitor formed for each of the DRAM cells in the silicon substrate. The semiconductor memory device may further include an n+-type buried capacitor plate formed in the silicon substrate and connected to the trench capacitor, and an n-type band layer formed in the silicon substrate and connected to the n+-type buried capacitor plate and corresponding one of the DRAM cells.
According to the present invention, DRAM devices merged with flash memory devices in a single chip do not require data refresh during sleep mode because data required by the system is stored in the flash memory and retrieved when the system returns to an active (or normal) mode.
A semiconductor memory device having structure of merged DRAM and flash memory devices also improves communication between memory and a central processing unit as well as communication between the DRAM and flash memory devices. Also, the existing DRAM built-in-self-test (BIST) technique allows DRAM to be tested at a high-speed without accessing all the internal nodes. Thus, the merged structure of DRAM and flash memory devices would be a low-cost solution of the problems in the conventional memory devices.
In the method of integrating the semiconductor memory device of the present invention, the process of integrating flash memory and DRAM devices may share as many process steps as possible so that the process is simplified and the manufacturing cost is reduced.